When a processor submits a request to a memory device, e.g., a Dynamic Random Access Memory (DRAM), the response from the memory device can be read by the processor after a delay of time, referred to as a “latency.” For example, a processor may issue a read request to a cache memory system; after a period of time, the cache memory system responds by placing the requested data on the bus. The processor can then receive the data from the bus after the latency expires. If the processor attempts to receive the data from the bus before the latency expires, the processor is likely to receive inaccurate and invalid data. Therefore when designing processors, it is crucial to take the memory latency into consideration.
In conventional computer-aided designs of processor or other integrated circuits, a lot of man and machine hours are needed to verify that the model of the integrated circuit is correct. For example, an architectural model, typically written by an engineering team, of the integrated circuit is used to define the functional requirements. Then a Register Transfer Level (RTL) model of the integrated circuit is then produced, typically by another engineering team, and the logic or the functionality of the RTL model is verified against the architectural model. Conventionally, the verification is performed with a “fixed latency” model (or so-called simulation environment), in which the memory latency values are set fixed. Actually, the amount of latency can vary depending on several factors, for example, the types of request. The amount of latency can also vary among the same types of request. Therefore, “fixed latency” is not accurate enough for the verification.
Based on the foregoing, there is a need for a more accurate and dynamic latency model to perform the verification of an integrated circuit.